1. Field of the Invention
The present invention relates to a cache memory apparatus and a microprocessor having a cache memory apparatus, and specifically relates to a technique for raising the speed of operation of writing data to a data cache memory.
2. Description of Related Art
A cache memory built in a microprocessor preliminarily stores data and instructions to be used frequently among data and instructions in a main memory, and makes a Central Processing Unit (CPU) accessible to these data and instructions at high speed. The cache memory built in the microprocessor includes a data cache memory (hereinafter abbreviated as data cache) and an instruction cache memory (hereinafter abbreviated as instruction cache). The cache memory is composed of a tag memory storing addresses as tag information, where data and instructions in the main memory are located and a data memory storing data and instructions corresponding to the tag information. The operation of the instruction cache including reading of a tag, tag comparison and judgment of hit or miss. In the case of a hit, the instruction corresponding to the tag is read. In the case of a miss, a re-register of the instruction from the main memory is performed. The operation of the data cache includes reading a tag, tag comparison and inversion of hit and miss. In case of a hit, a data read or data write of the data corresponding to the tag is performed. In the case of a miss, a re-register of the data from the main memory is performed.
The following provides a description of a configuration of a cache memory apparatus built in a conventional microprocessor according to the block diagram of FIG. 1.
In FIG. 1, numeral 101 designates an address register. When a new address is inputted to the address register 101 through an address bus (not illustrated), this address register 101 temporarily stores it. The number of rows selected int he lower-order part of the address is called the number of entries. This lower-order part of address is inputted to an entry decoder 103 which is installed in common in a data memory 106 and a tag memory 104. The entry decoder 103 selects entries of the tag memory 104 and the data memory 106 by decoding the lower-order part of address. The higher-order part of address is given to the tag memory 104 or to a comparator 107. Tag information in the tag memory 104 of the selected entry is also given to the comparator, and the tag information is compared with the higher-order part of the inputted address. The result of this comparison is given to a gate 108 to determine (1) whether or not the information outputted from the selected entry of the data memory 106 is to be outputted to a processing unit (not illustrated) as effective data or (2) whether or not the data from the processing unit is to be written to the selected data memory 106.
The conventional cache memory apparatus composed as described above operates as follows. The conventional cache memory decodes the lower-order part of an address in the entry decoder 103 in synchronism with a clock period and selects an entry in the tag memory 104. Tag information is read out from the selected entry of the tag memory 104 during the above-mentioned clock period. The read-out tag information is compared with the higher-order part of the inputted address by the comparator 107, and where these values coincide each other, it is said that the cache has hit, and a hit signal is generated. Also, where these values do not coincide each other, it is said that the cache has missed. Particularly, in the case of write operation, the cache hit is called write hit and the cache miss is called write miss.
FIG. 2 is a timing chart of a write operation of a conventional data cache. In a data cache write operation, when the cache has a hit (write hit) as a result of the tag comparison, data is written to the data memory 106 of the entry corresponding to the tag information. This means that read-out and comparison of the tag are performed and a hit signal is generated in synchronism with one clock period. In the next clock period next, data write to the data memory 106 of the row corresponding to the hit tag information is performed through the gate 108. In one example, in FIG. 1, tag information is read out from, e.g., the third row (the third entry) of the tag memory 104 in one clock period. This compared with the higher-order part of the address by the comparator 107, and, as a result, the hit signal becomes active. Then, the data is written to the third row (the third entry) of the data memory 104 in the next clock period. Data write cannot be performed in the data memory 106, while the tag information is read out from the tag memory 104. Also, while the data is written to the data memory 106.
As described above, a write operation of the conventional built-in cache memory, as shown in FIG. 2, necessitates a total of two clocks; one clock for read of tag information and tag comparison and one clock for re-write of the data corresponding to the above-mentioned tag information. Accordingly, there has been a problem that when write hits take place consecutively, two clock are required all the time, and thereby data access is delayed.
In general, the cache memory is used for sending and receiving data between an external memory device and a microprocessor at a high speed. In the case where the cache memory is located outside the microprocessor, because of delays between these units, a number of cycles are required also for data transfer from the cache memory to the microprocessor in comparison with the time of internal processing of the microprocessor. Accordingly, even when write operations are performed consecutively, the delay of the cache memory does not affect the whole functions very much. But in the case where the cache memory is built in the microprocessor, the delay required for data transfer from the cache memory to the microprocessor is small, and therefore the delay required for internal processing of the cache memory reduces the operating speed of the microprocessor and causes a reduction in speed of the whole function.